Cache memories store status bits with each data word. Status bits indicate whether their associated data word is valid, access privileges for that word and how recently that word has been accessed.
Status bits are typically updated each time the cache memory is accessed. Read-modify-writes dominate cache memory accesses because updated values of the status bits depend upon the data read out.
Caches memories are typically realized using static random access memories (SRAMs). SRAM cycle time is limited by the time it takes to perform a read cycle. In other words, SRAM cycle time is limited by the time required to perform precharge and a read access. In a high-performance system, where a memory access occurs every clock, the cycle time is exactly equal to the clock period Tp. Thus, the shorter the sum of the precharge time and the read access time the shorter Tp and the higher the clock frequency.
A read-modify-write cycle in prior SRAMs per force requires more time than a read cycle. During a read-modify-write cycle four operations take place in a single clock period, as compared to two operations during a read cycle. The four operations are:
1. Precharge PA1 2. Read Access PA1 3. Data Update PA1 4. Write Access to the same location as the read access.
FIG. 1 illustrates the waveforms for a read-modify-write cycle of a status bit in a prior SRAM. In FIG. 1, a "1" is read out and a "0" is written back. All four operations are performed during a single clock period.
As seen in FIG. 1, a read-modify-write cycle starts out with a precharge and a read access just like a simple read cycle. The third operation, data update, depends upon the data that was read out, and therefore, occurs only after the data has been read out. As the update is generally a complicated operation it typically takes place outside the cache memory in a dedicated circuit. The read-modify-write cycle ends with a write access to the same location as the read access.
Clearly, the additional time required to update the data and execute the write access make a read-modify-write cycle longer than a simple read. Read-modify-write cycles therefore determine the minimum SRAM clock period. Thus, the performance of prior SRAM cache memories is significantly less than would be possible if read-modify-write cycles were not part of normal operation.